Two-level pipelined systolic array graphics engine

The authors report a VLSI design of an advanced systolic array graphics (SAG) engine built from pipelined functional units which can generate realistic images interactively for high-resolution displays. They introduce a structured frame store system as an environment for the advanced SAG engine and present the principles and architecture of the advanced SAG engine. They introduce pipelined functional units into this SAG engine to meet the performance requirements. This is done by a formal approach where the original systolic array is represented at bit level by a finite, vertex-weighted, edge-weighted, directed graph. Two architectures built from pipelined functional units are described. A prototype containing nine processing elements was fabricated in a 1.6-¿m CMOS technolog

On frequency domain adaptive filters using the overlap-add method

The authors introduce a frequency-domain adaptive filter (FDAF) configuration using the overlap-add method which has the same complexity and convergence behavior as the overlap-save configuration. It is shown that an FDAF using the overlap-add method can be realized with the same number of DFTs (discrete Fourier transforms) as the FDAF using the overlap-save method. The overlap-add implementation of an FDAF with seven DFTs is described